Helped by reduction of cost and improvement of front-end wafer fabrication process, development of semiconductor devices has met the goal of reducing size of single chips of semiconductor devices while keeping same functions for the chips. Specifically, soldering balls may be formed on semiconductor wafers and then be directly applied to printed circuits.
Due to limitations of semiconductor wafer fabrication process or because of considerations by designers on multiple applications of a single integrated circuit, the positions of soldering balls of input and output terminals for electrical signal transmission need to be redefined during a semiconductor wafer-level packaging process.
FIG. 1 shows a schematic view of the structure of an exemplary semiconductor wafer with positions of soldering balls redefined using a method of the current technology. Referring to FIG. 1, after forming electric circuits on an active surface of a semiconductor wafer 101′, a plurality of electrodes 102′ and first passivation layers 103′ are formed on the surface of the semiconductor wafer 101′. The semiconductor wafer 101′ further includes a plurality of semiconductor chips 100′. The plurality of the semiconductor chips 100′ are connected with each other by scribe grooves 104a′. A second passivation layer 110′ is formed on each first passivation layer 103′ and an opening is formed in the second passivation layer 110′ near a corresponding electrode 102′. A re-distribution metal layer 210′ is formed on the surface of each second passivation layer 110′. Further, a third passivation layer 310′ is formed on the surface of each re-distribution metal layer 210′, and an opening is formed on the third passivation layer 310′ to expose the surface of the re-distribution metal layer 210′. An under bump metal layer 410′ is then formed to cover the bottom surface and the sidewall surface of the opening in each third passivation layer 310′. The under bump metal layer 410′ also covers a portion of the top surface of the third passivation layer near the opening. A spherical bump 510′ is then formed on the under bump metal layer 410′ by a pre-planting and backflow method. Further, a layer of adhesive film is attached on the back surface of the semiconductor wafer 101′ and the adhesive film layer is then cured. Finally, wafer-level packaged individual components 100′ are fully encapsulated after cutting.
However, the above method may cause interlayer separation between the bottom surface of the third passivation layer 310′ and the top surface of the re-distribution metal layer 210′ and, thus, may lead to subsequent failure of electrical performance of the product. The disclosed method and structure for wafer-level packaging is directed to solve one or more problems set forth above and other problems.